It is known that in modern data processing systems a plurality of processors may be used to increase performance. The processors have access to shared resources, for instance a working memory, through a system bus. In order to avoid conflicts and interference in system bus access, arbitration units are used. In case of concurrent bus access requests from a plurality of processors, the arbitration unit grants access to one processor at a time on the basis of predetermined priority criteria.
If the processors have the same features and functionality, it is advisable that they receive the same access priority right. Therefore, the arbitration unit operates according to a criterion known as "round robin". If a processor K among N ordered processor has just obtained access to the system bus, before granting access again to the same processor, it is determined whether processors K+1.fwdarw.N and 1.fwdarw.K-1 need access to the bus. If processor K+1 needs access to the bus, it receives access permission first. If processor K+1 does not need access to the bus, but processor K+2 does, then access is granted to processor K+2, and so on. If processor K again needs access to the bus, access is granted thereto only if no other processor needs access. In the case of two processors competing for access to the bus, the round robin criterion leads, at the extreme, to the alternative granting of access to each of the two processors, neither of which is privileged.
An arbitration unit which follows this criterion, may be, from a functional standpoint, one of three kinds:
1) Sequential. The arbitration unit polls, in timing sequence and according to a predetermined order, the presence of access requests to the system bus, one at a time, with a scanning cycle which requires a long time. For this reason, the sequential approach is generally no longer used. PA1 2) Synchronous. The several processors operate in synchronism and are clocked by a period timing signal which defines operative cycles or time frames. The access requests from the several processors are generated at predetermined times with a predetermined leading or lagging edge of the transitions of the timing signal. The arbitration unit, synchronously with the timing signal, samples the status of all the access requests and decides which of the processors has right of access. The arbitration time comprises two parts: the time of the decisional process required by the arbitration logic to grant one access since the sampling instant and the time elapsing from the generation of the access requests to the sampling instant. This kind of arbitration unit has the disadvantage that the arbitration process is not started as soon as an access request is generated, but is deferred until a predetermined sampling instant at which the status of the several access requests is stable. PA1 3) Asynchronous. Even if the several processors may operate in synchronism, they generally work asynchronously from each to the other. Bus access requests are randomly generated at unpredictable times, the one as to the others and to a possible periodic timing signal used by the arbitration unit. The arbitration unit may sample at high frequency the status of the several access requests. However, since the access requests may change status at the sampling instant, they may cause instability in the sampling circuits; therefore the decisional process must be delayed until the sampling circuits have taken a stable state. The same problem occurs in those arbitration units where the sampling of the bus access request is performed as soon as an access request is detected.
Other access requests, nearly simultaneous to the first one, may cause instability of the sampling circuits.